Last modified: Mon Jun 22 12:47:57 UTC+0200 2026 © A. Tarpai

The PE-bit

PE is bit0 of the CR0 register: Protection Enable. Same as PE in the 286 16-bit MSW.

         15              2    1    0
        +-  --  -+----+----+----+----+
        |        |    |    |    | PE |  286 MACHINE STATUS WORD
        +-  --  -+----+----+----+----+

 31                      2    1    0
+-  --  --  --  -+----+----+----+----+
|                |    |    |    | PE |  386+ CR0 Register
+-  --  --  --  -+----+----+----+----+

Setting PE = 1 apparently does nothing. But the CPU will operate differently based on PE set or cleared:

• What happens when a SEGMENT REGISTER IS WRITTEN
• Legacy 16-bit IVT vs IDT invoking mechanism for exceptions and interrupts
• Built-in Exception handling is different
• A bunch of p-mode instructions are invalid, when PE=0

PE can be set and cleared changing CPU operation by MOV CR0. Some restrictions apply, eg. paging requires PE set..etc. Note that the 286 LMSW (Load Machine Status Word) cannot clear PE, the 286 was unable to switch back to RM. This is also emulated on 386+ (PE stays set after LMSW, tested).

SR write

What the PE-bit means most importantly for the CPU is what happens when a SEGMENT REGISTER IS WRITTEN:

 WRITE SEG REG                   SEG REG DESCRIPTOR CACHE

+-----------+     PE=0      +-----------+-----------+------+      PE=1
|           |   ------->    |    BASE   |   LIMIT   | ATTR |    <-------  DESCRIPTOR IN MEMORY
+-----------+     x 16      +-----------+-----------+------+      FETCH

• when PE=0 the CPU simply moves SR value x 16 into BASE - thus emulating 8086-style segment base
• when PE=1 the written SR functions as a selector: an index into Descriptor Tables in main memory, which will start access check procedures, fetch and load the whole Segment Register Descriptor Cache