Last modified: Sun Sep 14 21:07:42 UTC+0200 2025 © A. Tarpai

386 MOVZX/MOVSX

386 new two-opcode (0F) instructions.

Moves and zero- or sign-extend R/M BYTE or WORD (w-bit) to operand-size(!) into REGISTER:

0F BE/BF  MOVSX reg, r/m
0F B6/B7  MOVZX reg, r/m


Opcode:

0F   1 0 1 1 S 1 1 W    MOD REG R/M

     S=0:  MOVZX   W=0:  extend byte
     S=1:  MOVSX   W=1:  extend word


             operand-size = 32               operand-size = 16
             D=1 or D=0 and 66h              D=0 or D=1 and 66h

            into 32-bit register            into 16-bit register

                                            REG-HI unchanged (.)


            W=0             r/m8            W=0             r/m8
            +--------------+----+           +---------+----+----+
MOVSX       | sssssssss <--|s   | BE        | . . . . |ss<-|s   | BE
            +--------------+----+           +---------+----+----+
            +--------------+----+           +---------+----+----+
MOVZX       | 000000000000 |    | B6        | . . . . |0000|    | B6
            +--------------+----+           +---------+----+----+
                     r32                                  r16



            W=1            r/m16            W=1            r/m16
            +---------+---------+           +---------+---------+
MOVSX       | sssss <-|s        | BF        | . . . . |         | BF(!)
            +---------+---------+           +---------+---------+
            +---------+---------+           +---------+---------+
MOVZX       | 0000000 |         | B7        | . . . . |         | B7(!)
            +---------+---------+           +---------+---------+
                     r32                                 r16

The only thing is when operand-size = 16, word is simply a move.